JESD79-4D is the peak of "simple" parallel DRAM. DDR5 adds massive complexity (DFE, PMICs, two independent sub-channels per DIMM).
The primary source for the full PDF is the JEDEC JESD79-4D Standards Page. Registration on the JEDEC site is typically required but free for individuals. jesd79-4d pdf
This section contains the AC and DC timing tables that memory controller designers live by. Key parameters include: JESD79-4D is the peak of "simple" parallel DRAM